This is the first post in a series of four covering various features of the newest version of the RSCAD software – Version 5.003.
Introducing GPES: a new FPGA-based power electronics solver
Real time power electronics simulation – custom converter modelling at timesteps in the sub-microsecond range
The all-new general power electronics solver (GPES) supports the real time modelling of power electronics on the RTDS Simulator’s GTFPGA Unit. The motivation behind the development of the GPES is to provide a highly flexible platform for modelling custom converter topologies with a reduced time step. The dedicated, FPGA-based hardware which runs GPES is capable of high-density calculation in parallel with the simulation running on the central RTDS Simulator hardware. Each GTFPGA Unit running GPES can support up to 128 nodes and 256 branches.
GPES uses the same LC modelling approach as the small timestep subnetworks (VSC bridge box) solved on the NovaCor’s processor – however, the GTFPGA Unit’s enhanced computational abilities mean that more nodes, more switches, and a reduced timestep are possible. The smaller time step will result in smaller L and C values for ON and OFF switching state representation which will result in more accurate representation of the switching losses for freely configurable converters.
Similarly to the small timestep subnetwork environment, GPES network development is done within a special GPES bridge box component in RSCAD (shown below). The new GPES tab in the Master Library contains a limited selection of components that can be used within the GPES bridge box. The GPES bridge box connects to a small timestep bridge box running on a NovaCor or PB5. That means the circuit running on GPES can be connected to a model running in the small timestep and exchange control signals with the small timestep. This way, any components required in the case which cannot be modeled on GPES (e.g. machines or dynamic loads) can be modelled in the small timestep as shown below. The GPES also has an Aurora interfacing block that allows firing pulses to be received directly from external controls.
The GTFPGA Unit running GPES is connected with the main RTDS Simulator hardware via fibre cable (connected from the rear of the GTFPGA Unit to the rear of the NovaCor chassis or GTWIF-based rack running the simulation) as shown in the below diagram.
For more information on GPES or other features of RSCAD Version 5.003, please email firstname.lastname@example.org.