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Power hardware in the loop (PHIL) simulation involves the real-time simulation environment exchanging power with real, physical power hardware, such as renewable energy hardware, electric vehicles, batteries, motors and loads. The RTDS Simulator has been successfully used for performing power hardware in the loop (PHIL) experiments in a wide range of applications.

PHIL simulation is often used for studying the impacts of integrating distributed energy resources in transmission and distribution grids. Here are a few examples of PHIL projects that have been carried out by our customers:

  • The testing of motors of electric ships and motor drives in the MW range
  • Virtual Synchronous Generator (VSG) testing
  • Testing of variable-speed wind turbine generators in the MW range
  • Three-phase power converter synchronization study
  • Photovoltaic inverter (PV) testing

Case Study: PHIL Simulation with a PV Inverter using the RTDS Simulator

Power Hardware in the Loop (PHIL) simulation enables the real time testing of devices in a controlled environment before they are connected to the actual physical system. A software model of the actual system where the physical device will operate is developed on the RTDS Simulator, and voltage and current signals are exchanged with the device. The interface between the RTDS Simulator and the device under test should be carefully considered with respect to the computation time step of the RTDS Simulator, which determines the total delay in the PHIL interface. The method used to exchange the voltage and current signals in the PHIL interface and the power ratings of the test device and selected amplifier are also critical considerations.

An increasingly popular application of PHIL simulations is the testing of grid-connected photovoltaic inverters, as shown in Figure 1. Digital to Analog converters included as part of the RTDS Simulator (via the GTAO card) provide analog signals scaled down to electronic levels within ±10Vpk. These signals are provided as input to an amplifier which provides the required voltage, current, and frequency levels to the inverter. Sensors measure the voltage or current signals obtained from the inverter, which are then passed through an Analog to Digital converter (via the GTAI card) and sent back to the RTDS Simulator to close the loop. Filters implemented in hardware/software are required to eliminate noise in the PHIL interface. The filter design and parameters should be selected to offer an acceptable trade-off between improved stability and reasonable accuracy of the PHIL simulation.

 PHIL Interface between a RTDS and a Device Under Test

Figure 1: PHIL Interface between a RTDS and a Device Under Test (Inverter)

A test setup of a PHIL interface with a 255W PV inverter and a 1kVA linear voltage amplifier is shown in Figure 2. This test setup was carried out at the RTDS Technologies headquarters. The DC side of the inverter is connected to a solar panel with a metal halide light source used as a sunlight simulator. The AC side of the inverter is connected to the amplifier output terminal which provides the grid simulation at 240Vrms, 60Hz. The inverter current measured by the amplifier is sent back to the simulated grid in the RTDS Simulator.

PHIL simulation with a Photovoltaic Micro Inverter

Figure 2: Test setup of a PHIL simulation with a Photovoltaic Micro Inverter

Figure 3 shows the inverter current observed in the RTDS Simulator superimposed with noise from the PHIL interface. A low pass filter is used to eliminate the noise on current signal. The filter improves the stability of the PHIL simulation but attenuates the magnitude of the current signal and adds an additional time delay. The magnitude attenuation and time delay introduced by the filter is determined by the selected cut off frequency. Figure 4 shows a 50% difference in the inverter power computed in the RTDS Simulator when the filter cut-off frequency is changed from 500Hz to 500kHz. Lower cut-off frequencies result in higher time delays and increased magnitude attenuation, which impacts the accuracy of the PHIL simulation observed in the RTDS Simulator.

Inverter current in the RTDS

Figure 3: Inverter current in the RTDS

Inverter power observed in the RTDS

Figure 4: Inverter power observed in the RTDS increases by 50% when filter cutoff is changed from 500Hz to 5kHz

PHIL simulation enables the testing of devices with unknown circuit topologies under various contingency scenarios. Figure 5 shows the inverter’s response to a line to ground fault simulated with the RTDS Simulator. The current response shows that the inverter remains grid-connected when the fault duration is 5 cycles. The point at which the inverter disconnects from the grid can be seen when the fault duration was increased to 60 cycles. It should be noted that the contingency scenarios to be tested in the PHIL interface should be within the protection limits of the device under test as well as the amplifier ratings in order to prevent unstable operation.


Figure 5: Inverter AC current response to a 5 cycle and 60 cycle, line to ground fault condition simulated in the RTDS


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